Pedro Villar Castro
Profesor Titular de Universidad
E.T.S. de Ingenierías Informática y de Telecomunicación
C/ Periodista Daniel Saucedo Aranda S/N
18071
Granada
958240637
Timetable for personal attention
First semester
Day
Timetable
Place
Wednesday
9:30 - 13:30
Etsiit 3ª p despacho 39
Thursday
9:30 - 11:30
Etsiit 3ª p despacho 39
Second semester
Day
Timetable
Place
Tuesday
10:00 - 13:00
Etsiit 3ª p despacho 39
Wednesday
10:00 - 13:00
Etsiit 3ª p despacho 39
Teaching
Bachelor's degree in computer engineering
Master's degree in business process management and technologies
Business process modelling and analysis - analysis and inference in business processes
Master's degree in business process management and technologies
Business process modelling and analysis - analysis and inference in business processes